1. Field
The described technology relates to a delayed locked loop (DLL), and more particularly, to a coarse lock detector for a DLL.
2. Description of the Related Technology
Generally, a semiconductor integrated circuit operates using clocks to control its operating speed. Accordingly, the semiconductor integrated circuit includes a clock buffer to buffer clocks input from an external source. In some cases, the semiconductor integrated circuit uses a delayed locked loop (DLL) circuit or a phase-locked loop (PLL) circuit to generate and use an internal clock whose phase difference from an external clock has been corrected.
In particular, DLLs are being widely used as zero delay buffers due to their superior jitter characteristics and better stability than PLLs. However, a conventional DLL is likely to have a stuck problem or harmonic lock when operating at high speed.
FIG. 1 illustrates a structure of a conventional DLL including a coarse lock detector 11. Referring to FIG. 1, a plurality of delay elements 15 generates a set of multiphase clocks PH[1] through PH[15] by incrementally delaying an input reference clock CLK_IN. The coarse lock detector 11 receives the input reference clock CLK_IN and a plurality of multiphase clocks. In FIG. 1, some (PH[5], PH[7], PH[9], PH[11], PH[13] and PH[15]) of the multiphase clocks PH[1] through PH[15] generated by the delay elements 15 are input to the coarse lock detector 11. Within one cycle of the input reference clock CLK_IN, the coarse lock detector 11 continuously counts the number of rising edges of the received multiphase clocks and determines whether a phase of the rising edge of each multiphase clock lags behind a phase of the input reference clock CLK_IN, leads the phase of the input reference clock CLK_IN, or is locked to the phase of the input reference clock CLK_IN.
When the coarse lock detector 11 determines that the phase of the rising edge of each multiphase clock lags behind the phase of the input reference clock CLK_IN, phase locking cannot be achieved since a delay chain is too slow. Therefore, the coarse lock detector 11 generates an UP signal indicating a direction in which the frequency should be adjusted. On the other hand, when the coarse lock detector 11 determines that the phase of the rising edge of each multiphase clock leads the phase of the input reference clock CLK_IN, phase locking cannot be achieved since the delay chain is too fast. Therefore, the coarse lock detector 11 generates a DOWN signal. That is, frequency locking can be achieved by adjusting the frequency by using the UP or DOWN signal.
The stuck problem and harmonic lock are considerations that must be taken into account when designing a DLL and can be solved using a coarse lock detector. However, a conventional coarse lock detector that samples multiphase clocks cannot operate at high speed.